View 74LS181_309381.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

DM74LS181 4-Bit Arithmetic Logic Unit
October 1988 Revised April 2000
DM74LS181 4-Bit Arithmetic Logic Unit
General Description
The DM74LS181 is a 4-bit Arithmetic Logic Unit (ALU) which can perform all the possible 16 logic operations on two variables and a variety of arithmetic operations.
Features
s Provides 16 arithmetic operations: add, subtract, compare, double, plus twelve other arithmetic operations s Provides all 16 logic operations of two variables: exclusive-OR, compare, AND, NAND, OR, NOR, plus ten other logic operations s Full lookahead for high speed arithmetic operation on long words
Ordering Code:
Order Number DM74LS181N Package Number N24A Package Description 24-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-010, 0.600 Wide
Logic Symbols
Active High Operands
Connection Diagram
Active Low Operands
Pin Descriptions
Pin Names A0-A3 B0-B3 S0-S3 M Cn F0-F3
VCC = Pin 24 GND = Pin 12
Description Operand Inputs (Active LOW) Operand Inputs (Active LOW) Function Select Inputs Mode Control Input Carry Input Function Outputs (Active LOW) Comparator Output Carry Generate Output (Active LOW) Carry Propagate Output (Active LOW) Carry Output
A=B G P Cn+4
(c) 2000 Fairchild Semiconductor Corporation
DS009821
www.fairchildsemi.com
DM74LS181
Functional Description
The DM74LS181 is a 4-bit high speed parallel Arithmetic Logic Unit (ALU). Controlled by the four Function Select inputs (S0-S3) and the Mode Control input (M), it can perform all the 16 possible logic operations or 16 different arithmetic operations on active HIGH or active LOW operands. The Function Table lists these operations When the Mode Control input (M) is HIGH, all internal carries are inhibited and the device performs logic operations on the individual bits as listed. When the Mode Control input is LOW, the carries are enabled and the device performs arithmetic operations on the two 4-bit words. The device incorporates full internal carry lookahead and provides for either ripple carry between devices using the Cn+4 output, or for carry lookahead between packages using the signals P (Carry Propagate) and G (Carry Generate). In the ADD mode, P indicates that F is 15 or more, while G indicates that F is 16 or more. In the SUBTRACT mode, P indicates that F is zero or less, while G indicates that F is less than zero. P and G are not affected by carry in. When speed requirements are not stringent, it can be used in a simple ripple carry mode by connecting the Carry output (Cn+4) signal to the Carry input (Cn) of the next unit. For high speed operation the device is used in conjunction with the 9342 or 93S42 carry lookahead circuit. One carry lookahead package is required for each group of four DM74LS181 devices. Carry lookahead can be provided at various levels and offers high speed capability over extremely long word lengths. The A = B output from the device goes HIGH when all four F outputs are HIGH and can be used to indicate logic equivalence over four bits when the unit is in the subtract mode. The A = B output is open-collector and can be wiredAND with other A = B outputs to give a comparison for more than four bits. The A = B signal can also be used with the Cn+4 signal to indicate A > B and A < B. The Function Table lists the arithmetic operations that are performed without a carry in. An incoming carry adds a one to each operation. Thus, select code LHHL generates A minus B minus 1 (2s complement notation) without a carry in and generates A minus B when a carry is applied. Because subtraction is actually performed by complementary addition (1s complement), a carry out means borrow; thus a carry is generated when there is no underflow and no carry is generated when there is underflow. As indicated, this device can be used with either active LOW inputs producing active LOW outputs or with active HIGH inputs producing active HIGH outputs. For either case the table lists the operations that are performed to the operands labeled inside the logic symbol.
Function Table
Mode Select Inputs Logic S3 L L L L L L L L H H H H H H H H S2 L L L L H H H H L L L L H H H H S1 L L H H L L H H L L H H L L H H S0 L H L H L H L H L H L H L H L H A AB A+B Logic 1 A+B B AB A+B AB AB B A+B Logic 0 AB AB A (M = H) Active LOW Operands & Fn Outputs Arithmetic (Note 2) (M = L) (Cn = L) A minus 1 AB minus 1 AB minus 1 minus 1 A plus (A + B) AB plus (A + B) A minus B minus 1 A+B A plus (A + B) A plus B AB plus (A + B) A+B A plus A (Note 1) AB plus A AB minus A A A A+B AB Logic 0 AB B AB AB A+B AB B AB Logic 1 A+B A+B A Logic (M = H) A A+B A+B minus 1 A plus AB (A + B) plus AB A minus B minus 1 AB minus 1 A plus AB A plus B (A + B) plus AB AB minus 1 A plus A (Note 1) (A + B) plus A (A + B) plus A A minus 1 Active HIGH Operands & Fn Outputs Arithmetic (Note 2) (M = L) (Cn = H)
Note 1: Each bit is shifted to the next most significant position. Note 2: Arithmetic operations expressed in 2s complement notation.
www.fairchildsemi.com
2
DM74LS181
Logic Diagram
3
www.fairchildsemi.com
DM74LS181
Absolute Maximum Ratings(Note 3)
Supply Voltage Input Voltage Operating Free Air Temperature Range Storage Temperature Range 7V 7V 0C to +70C -65C to +150C
Note 3: The "Absolute Maximum Ratings" are those values beyond which the safety of the device cannot be guaranteed. The device should not be operated at these limits. The parametric values defined in the Electrical Characteristics tables are not guaranteed at the absolute maximum ratings. The "Recommended Operating Conditions" table will define the conditions for actual device operation.
Recommended Operating Conditions
Symbol VCC VIH VIL IOH IOL TA Supply Voltage HIGH Level Input Voltage LOW Level Input Voltage HIGH Level Output Current LOW Level Output Current Free Air Operating Temperature 0 Parameter Min 4.75 2 0.8 -0.4 8 70 Nom 5 Max 5.25 Units V V V mA mA C
Electrical Characteristics
over recommended operating free air temperature range (unless otherwise noted) Symbol VI VOH VOL Parameter Input Clamp Voltage HIGH Level Output Voltage LOW Level Output Voltage II Input Current @ Max Input Voltage Conditions VCC = Min, II = -18 mA VCC = Min, IOH = Max, VIL = Max VCC = Min, IOL = Max, VIH = Min IOL = 4 mA, VCC = Min VCC = Max, VI = 7V M input An, Bn Sn Cn IIH HIGH Level Input Current VCC = Max, VI = 2.7V M input An, Bn Sn Cn IIL LOW Level Input Current VCC = Max, VI = 0.4V M input An, Bn Sn Cn IOS Short Circuit Output Current ICC Supply Current VCC = Max (Note 5) VCC = Max, Bn, Cn = GND Sn, M, An = 4.5V
Note 4: All typicals are at VCC = 5V, TA = 25C. Note 5: Not more than one output should be shorted at a time, and the duration should not exceed one second.
Min
Typ (Note 4)
Max -1.5
Units V V
2.7 0.35 0.25 0.5 0.4 0.1 0.3 0.4 0.5 20 60 80 100 -0.4 -1.2 -1.6 -2.0 -20 -100
V
mA
A
mA
mA
37
mA
www.fairchildsemi.com
4
DM74LS181
Switching Characteristics
VCC = 5V, TA = 25C Symbol tPLH tPHL tPLH tPHL tPLH tPHL tPLH tPHL tPLH tPHL tPLH tPHL tPLH tPHL tPLH tPHL tPLH tPHL tPLH tPHL tPLH tPHL tPLH tPHL Parameter Propagation Delay Cn to Cn+4 Propagation Delay Cn to F Propagation Delay A or B to G (Sum) Propagation Delay A or B to G (Diff) Propagation Delay A or B to P (Sum) Propagation Delay A or B to P (Diff) Propagation Delay Ai or Bi to Fi(Sum) Propagation Delay Ai or Bi to Fi(Diff) Propagation Delay A or B to F (Logic) Propagation Delay A or B to Cn+4 (Sum) Propagation Delay A or B to Cn+4 (Diff) Propagation Delay A or B to A = B M, S1, S2 = GND; S0, S3 = 4.5V M, S0, S3 = GND; S1, S2 = 4.5V M, S0, S3 = GND; S1, S2 = 4.5V; RL = 2 k to 5.0V M, S1, S2 = GND; S1, S3 = 4.5V M, S0, S3 = GND; S1, S2 = 4.5V M, S1, S2 = GND; S0, S3 = 4.5V M, S0, S3 = GND; S1, S2 = 4.5V M, S1, S2 = GND; S0, S3 = 4.5V M, S0, S3 = GND; S1, S2 = 4.5V M = 4.5V M = GND M = GND Conditions CL = 15 pF Min Max 27 20 26 20 29 23 32 26 30 30 30 33 32 25 32 33 33 29 38 38 41 41 50 62 Units ns ns ns ns ns ns ns ns ns ns ns ns
Sum Mode Test Table 1
S0 = S3 = 4.5V, S1 = S2 = M = 0V Input Symbol Under Test
Function Inputs
Other Input Same Bit Apply 4.5V Apply GND None Apply 4.5V Remaining A and B Apply GND Cn Cn Remaining A and B, Cn Fi Fi P Other Data Inputs Output Under Test
tPLH tPHL tPLH tPHL tPLH tPHL tPLH tPHL tPLH tPHL tPLH tPHL tPLH tPHL tPLH tPHL tPLH tPHL
Ai Bi A
Bi Ai B
None
Remaining A and B
None
None
B
A
None
None
Remaining A and B, Cn
P
A
None
B
Remaining B
Remaining A, Cn Remaining A, Cn Remaining A, Cn Remaining A, Cn All B
G
B
None
A
Remaining B
G
A
None
B
Remaining B
Cn+4 Cn+4 Any F or Cn+4
B
None
A
Remaining B
Cn
None
None
All A
5
www.fairchildsemi.com
DM74LS181
Diff Mode Test Table 2
S1 = S2 = 4.5V, S0 = S3 = M = 0V Input Symbol Under Test
Function Inputs
Other Input Same Bit Apply 4.5V Apply GND B Apply 4.5V Remaining A Apply GND Remaining B, Cn Remaining B, Cn Remaining A and B, Cn P Fi Fi Other Data Inputs Output Under Test
tPLH tPHL tPLH tPHL tPLH tPHL tPLH tPHL tPLH tPHL tPLH tPHL tPLH tPHL tPLH tPHL tPLH tPHL tPLH tPHL tPLH tPHL
A
None
B
A
None
Remaining A
A
None
B
None
B
A
None
None
Remaining A and B, Cn
P
A
B
None
None
Remaining A and B, Cn
G
B
None
A
None
Remaining A and B, Cn
G A=B A=B Cn+4 Cn+4 Cn+4
A
None
B
Remaining A
Remaining B, Cn Remaining B, Cn Remaining A and B, Cn
B
A
None
Remaining A
A
B
None
None
B Cn
None None
A None
None All A and B
Remaining A and B, Cn None
Logic Mode Test Table 3
S1 = S2 = M = 4.5V, S0 = S3 = 0V Input Symbol Under Test Apply 4.5V tPLH tPHL tPLH tPHL B A A B
Function Inputs
Other Input Same Bit Apply GND None Apply 4.5V None Apply GND Remaining A and B, Cn None None Remaining A and B, Cn Any F Any F Other Data Inputs Output Under Test
www.fairchildsemi.com
6
DM74LS181 4-Bit Arithmetic Logic Unit
Physical Dimensions inches (millimeters) unless otherwise noted
24-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-010, 0.600 Wide Package Number N24A
Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications. LIFE SUPPORT POLICY FAIRCHILD'S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. 7 2. A critical component in any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. www.fairchildsemi.com
www.fairchildsemi.com

▲Up To Search▲

Price & Availability of 74LS181

	To Download 74LS181 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .